In a multi-level memory device, cells generally assume more than two logic states and thus may store more than one bit of information. In a four-level memory cell, each cell is capable of storing two-bit of information by fixing its threshold voltage according to the distribution depicted in FIG. 1. The state ‘11’ is stored by an erasing operation, and the other three states (‘10’, ‘01’ and ‘00’) are stored by a programming operation.
In order to avoid the known problems of “read disturb” and “retention,” an error correction code (ECC) technique is used by reserving a number of memory cells, commonly called correction cells, the content of which is determined as a function of data stored in the cells of the array, in order to correct an eventual loss of information. For example, in NOR FLASH memory devices in which a page of data at the time, typically having 4, 8 or 16 words, is read, for each page there is a certain number k of correction cells; the larger the value of k, the larger the number of bits that can be corrected on the page.
A drawback of this approach is that the ECC limits the operations that may be executed by users. In a NOR FLASH memory device, it is possible to carry out a program operation on a single cell, but an erase operation may be executed in parallel on all the cells of a sector.
The presence of cells for storing the correction bit ECC may not allow users to carry out a program operation on each page without erasing the whole memory sector. Indeed, a program operation (1→0) may imply erasing (0→1) in at least a correction cell. As stated before, this may not be done on a single cell of a NOR FLASH memory device, but on the whole addressed sector to which the cell belongs. As a consequence, the use of ECCs in NOR FLASH memory devices may strongly limit the so-called “bit manipulation,” i.e. the possibility of programming single bits of the memory.
A three-level memory device that occupies a silicon area slightly larger than that of four-level memory devices of the same storage capacity, but that practically avoids the above remarked ECC limitations, is described in the Italian patent application VA2006A000065, in the name of the same applicant.
The disclosed device employs three-level cells in which each pair of cells is to store a string of three bits and comprises a coding circuit and a decoding circuit for converting, in a write operation, the strings of three bits to be stored in strings of two ternary values to be written in respective pairs of three-level cells and vice versa during a read operation.
The possible states that may be assumed by the cells are three, thus the relative distributions of the read thresholds, as depicted in FIG. 2, may be relatively farther away from the voltage levels at which the “read disturb” and “retention” phenomena become more severe.
As may be common to all multi-level memory devices, the disclosed three-level memory device is burdened by problems that may be created by accidental supply voltage interruptions or significant voltage drops during programming operations.
In order to better understand this peculiar challenge faced by multi-level memory devices, let us refer to the scheme of FIG. 3 for a four-level cell capable of storing two bits.
Supposing that an initially erased cell (11) is to be programmed in the state 01, this operation is compliant with “bit manipulation” rules because only one bit may be programmed. The threshold voltage Vth of the cell may be incremented by applying program pulses to the cell, until its threshold is incremented to a value comprised in the distribution curve relative to the level 01.
As schematically illustrated in FIG. 3, an accidental voltage drop or supply interruption sufficient to stop the program operation may occur when the threshold voltage Vth is still within the distribution corresponding to the level 10. In this case, a transition 11→10 takes place and it may be no longer possible to further program the cell to the state 01 because the transition 10→01, even if physically possible, violates the “bit manipulation” rules and is impeded by the control circuits of the memory. Repeating the same program operation would not solve the problem, because the cell would go from state 10 to state 00.
An approach would be that of carrying out an erase operation for bringing the cell from the state 10 back to the state 11 and then repeating the program operation. This may be inconvenient, particularly in NOR FLASH memory devices, wherein erase operations may be carried out on a whole memory sector and not on a single cell. In practice, in order to comply with the “bit manipulation” requisites, a bit at logic level 1 may be programmed to the logic level 0 but the opposite cannot be done through a program operation.
For this reason, when it is of paramount importance that data be correctly stored even in the event of a power failure during program operations, adjacent pairs of bits may be programmed, that is equivalent to programming a four-level cell to the state 00. This is possible without violating the rules of “bit manipulation” because a four-level cell may be programmed in the state 00 whether it is in the state 10 or in the state 01.
In the case of a three-level cell, it may be easily recognized that an accidental power failure may be dangerous if it took place during a program operation from A to C and if the threshold voltage of the cell at the moment of the failure corresponds to the level B.
Therefore, a management method of a memory device including three-level cells may ensure that an eventual interruption of a program operation may not leave pairs of memory cells in an intermediate program state from which it would not be possible to reach the desired final state without violating the rules of “bit manipulation.”